Title :
A 95 mW, 10 b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme
Author :
Matsuura, T. ; Hotta, M. ; Usui, K. ; Imaizumi, E. ; Ueda, S.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A very-low-power, 95 mW, 10 b 15 MHz CMOS pipelined fully differential A/D converter (ADC) is fabricated using analog double sampling. Excellent power reduction is achieved using this sampling technique and a 3.3 V supply voltage design for comparator circuits. The 5 V internal supply is generated by an on-chip 3.3 V to 5 V charge pumping voltage generator. The fully differential approach is compatible with this type of implementation. The amplifier has a triple cascode configuration to achieve a gain of 80 dB. The converter exhibits good performance at 15 MHz, very good input bandwidth of 7.53 MHz at the 15 MHz conversion rate, and good linearity. Excellent power dissipation is observed.<>
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; sample and hold circuits; 10 bit; 15 MHz; 3.3 V; 5 V; 7.53 MHz; 80 dB; 95 mW; CMOS pipelined fully differential A/D converter; analog double-sampled pipelining scheme; charge pumping voltage generator; input bandwidth; internal supply; linearity; low-power CMOS ADC; power dissipation; power reduction; supply voltage; triple cascode configuration; Circuits; Clocks; Digital signal processing; Energy consumption; Error correction; Laboratories; Pipeline processing; Power amplifiers; Signal sampling; Voltage;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229273
