A 10 b 300 MHz interpolated-parallel A/D converter

Author

Kimura, H. ; Matsuzawa, A. ; Nakamura, T. ; Sawada, S.

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

94

Lastpage

95

Abstract

A 10-b A/D converter with a maximum conversion frequency of 300 MHz, which is four times higher than that for reported 10-b A/D converters, is developed. With an interpolated parallel conversion scheme, the severe requirements for V/sub be/ mismatch can be reduced significantly. It is possible to implement an ultrahigh f/sub T/ of a 25 GHz bipolar transistor to the parallel A/D converter with small differential nonlinearity. SNR of 48 dB and total harmonic distortion of 47 dB at the input frequency of 50 MHz can be achieved. By means of folded differential logic circuits, the number of logic gates is reduced to half that of the conventional approach. The chip is composed of 36 K elements and consumes 4.0 W on a 9.0 mm*4.2 mm die.<>

Keywords

analogue-digital conversion; bipolar integrated circuits; 10 bit; 25 GHz; 300 MHz; 4 W; 50 MHz; SNR; bipolar transistor; folded differential logic circuits; input frequency; interpolated parallel conversion scheme; interpolated-parallel A/D converter; maximum conversion frequency; power consumption; small differential nonlinearity; total harmonic distortion; ultrahigh cutoff frequency; Capacitance; Differential amplifiers; Frequency conversion; Interpolation; Latches; Logic circuits; Master-slave; Production; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229275

Filename

229275