• DocumentCode
    3267757
  • Title

    Input collapse of CMOS logic gates with a series-connected MOSFET chain

  • Author

    Jiang, Xueping ; Jayasumana, Anura P.

  • Author_Institution
    Lattice Semicond. Corp, San Jose, CA, USA
  • Volume
    3
  • fYear
    2004
  • fDate
    18-21 Oct. 2004
  • Firstpage
    1928
  • Abstract
    We propose a generic series-connected MOSFET chain model (SMCM) extending the PDSMM, to describe the peculiar DC characteristics of a series MOSFET chain. Initial state propagation delays (ISPD) are defined as propagation delays due to initial states of intermediate nodes of a series-connected MOSFET chain. Two extreme and important ISPD, called as fast ISPD and slow ISPD, are introduced. The effect of input patterns of CMOS logic gates on propagation delays in the two ISPD is discussed. Finally, an efficient mapping algorithm for every possible input pattern to an equal input ramp is introduced.
  • Keywords
    CMOS logic circuits; delays; logic design; CMOS logic gates; DC characteristics; PDSMM; fast ISPD; initial state propagation delays; input collapse; input pattern; input ramp; intermediate nodes; mapping algorithm; series-connected MOSFET chain; slow ISPD; CMOS digital integrated circuits; CMOS logic circuits; Equivalent circuits; Inverters; Logic gates; MOSFET circuits; Parasitic capacitance; Propagation delay; Semiconductor device modeling; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
  • Print_ISBN
    0-7803-8511-X
  • Type

    conf

  • DOI
    10.1109/ICSICT.2004.1435215
  • Filename
    1435215