Title :
Bipartition for 2.5-D floorplanning based on corner block list representation
Author :
Xu, Ning ; Wei, Shoujun ; Hong, Xianlong ; Dong, Sheqin
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
This paper investigates a 3D die-stacking based VLSI integration strategy, so-called 2.5D integration, which can potentially overcome many problems stumbling the development system-on-chip (SoC), such as interconnect delay of monolithic problems due to scaling and increasing chip area. We present an approach using bipartitioning for 2.5D floorplanning based on corner block list representation. Experimental results show significant wirelength reduction compared to monolithic floorplanning.
Keywords :
VLSI; circuit layout CAD; logic partitioning; system-on-chip; 2.5D floorplanning; 2.5D integration; 3D die-stacking; SoC; VLSI integration strategy; bipartitioning; chip area; corner block list representation; interconnect delay; monolithic problems; scaling; system-on-chip; wirelength reduction; Computer science; Delay; Electronic design automation and methodology; Integrated circuit interconnections; Large scale integration; Partitioning algorithms; Power system interconnection; Routing; Very large scale integration; Wires;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435216
