Title :
A 1-volt, 2.5-mW, 2.4-GHz frequency synthesizer in 0.35-µm CMOS technology
Author :
Tan, Jun ; Lian, Yong
Author_Institution :
ECE Dept., Nat. Univ. of Singapore, Singapore, Singapore
Abstract :
In this paper, we present a low voltage, low power, 2.4-GHz frequency synthesizer designed in 0.35-μm CMOS technology. The frequency synthesizer is implemented with an Integer-N phase-locked loop (PLL). The PLL can achieve a frequency tuning step of 1-MHz and is capable of covering the whole 2.4-GHz ISM band. The voltage controlled oscillator (VCO) output frequency is firstly divided by a novel tri-modulus current-mode prescaler. The prescaler output is converted to rail-to-rail swing and drives the true single phase clocked register (TSPC) CMOS counters. The loop filter is designed to be 2nd order and implemented off-chip with passive devices. The post-layout simulation results show that the phase noise of the VCO is -107 dBc/Hz at 1 MHz offset, and the PLL reference spur level of the PLL is below -50 dBc.
Keywords :
CMOS integrated circuits; UHF integrated circuits; frequency synthesizers; low-power electronics; phase locked loops; prescalers; voltage-controlled oscillators; CMOS technology; ISM band; PLL; VCO; frequency 2.4 GHz; frequency synthesizer; integer-N phase-locked loop; loop filter; low power; low voltage; passive devices; power 2.5 mW; rail-to-rail swing; size 0.35 μm; tri-modulus current-mode prescaler; true single phase clocked register CMOS counters; voltage 1 V; voltage controlled oscillator; CMOS technology; Clocks; Counting circuits; Frequency conversion; Frequency synthesizers; Low voltage; Phase locked loops; Rail to rail outputs; Tuning; Voltage-controlled oscillators;
Conference_Titel :
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4668-1
Electronic_ISBN :
978-1-4244-4669-8
DOI :
10.1109/PRIMEASIA.2009.5397460