Title :
A bipolar 1.5 Gb/s monolithic phase-locked loop for clock and data extraction
Author :
Wu, J.-T. ; Walker, R.C.
Author_Institution :
Hewlett-Packard Co., San Jose, CA, USA
Abstract :
The design of a monolithic phase-locked loop (PLL) used in a gigabit serial data link interface for clock and data extraction is described. Implemented in a triple-metal 25-GHz f/sub t/ bipolar process and consuming 85 mA from a 5 V-supply, the PLL has a wide frequency acquisition range, from 600 MHz to 1.5 GHz, and a recovered clock phase jitter of less than 18.3 ps r.m.s. The PLL requires only one external component (the loop filter capacitor) needs no adjustment, and is suitable for large-scale integration.<>
Keywords :
bipolar integrated circuits; data communication equipment; digital communication systems; large scale integration; mixed analogue-digital integrated circuits; phase-locked loops; 1.5 Gbit/s; 25 GHz; 5 V; 600 MHz to 1.5 GHz; 85 mA; PLL; clock extraction; data extraction; gigabit serial data link interface; large-scale integration; loop filter capacitor; monolithic phase-locked loop; triple metal bipolar process; Circuits; Clocks; Data mining; Flip-flops; Jitter; Low pass filters; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229282
