An 8*8 ATM switch LSI with shared multi-buffer architecture

Author

Notani, H. ; Kondoh, H. ; Hayashi, I. ; Yamanaka, H. ; Saito, H. ; Matsuda, Y. ; Nakaya, M.

Author_Institution

Mitsubishi Electric Corp., Itami, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

74

Lastpage

75

Abstract

An ATM switch LSI with a shared multibuffer architecture is proposed. With this architecture, a fourfold speed improvement is achieved in accessing buffer memories as compared to conventional shared-buffer-type switches, and high buffer memory utilization efficiency is also realized. This switch LSI is designed to operate at 100 MHz, using 0.8- mu m BiCMOS technology. Eight switch LSIs at 78-MHz operation construct a 622-Mb/s 8*8 ATM switching system with a buffer size of 8*128 ATM cells.<>

Keywords

BiCMOS integrated circuits; asynchronous transfer mode; buffer storage; digital integrated circuits; electronic switching systems; large scale integration; multiplexing equipment; semiconductor switches; 0.8 micron; 622 Mbit/s; 78 MHz; ATM switch LSI; BiCMOS technology; buffer memories; shared multibuffer architecture; switching system; Asynchronous transfer mode; B-ISDN; BiCMOS integrated circuits; Buffer storage; Clocks; Communication switching; Large scale integration; Switches; Switching systems; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229284

Filename

229284