Title :
High-speed low-power Darlington ECL circuit
Author :
Chuang, C.T. ; Chin, K. ; Lu, P.F. ; Shin, H.J.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
An emitter coupled logic (ECL) circuit with a Darlington configured dynamic current source and an active-pull-down emitter-follower stage for low-power high-speed gate array application is presented. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A self-biasing scheme for the dynamic current source and the active-pull-down transistor, with no additional devices and power in the biasing circuit, is described. Based on a 0.8- mu m double-poly self-aligned bipolar technology at a power consumption of 1.0-mW/gate, the circuit offers 28% improvement in the loaded delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.<>
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; 0.8 micron; 1 W; Darlington ECL circuit; active-pull-down transistor; double-poly; dynamic current source; emitter coupled logic; emitter-follower stage; high-speed gate array; low-power; power consumption; scaling; self-aligned bipolar technology; self-biasing scheme; switching transient; Delay; Energy consumption; Logic devices; Power dissipation; Resistors; Steady-state; Switched capacitor circuits; Switches; Switching circuits; Voltage;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229286
