DocumentCode :
3267893
Title :
Sub-1-V swing bus architecture for future low-power ULSIs
Author :
Nakagome, Y. ; Itoh, K. ; Isoda, M. ; Takeuchi, K. ; Aoki, M.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fYear :
1992
fDate :
4-6 June 1992
Firstpage :
82
Lastpage :
83
Abstract :
Reducing the operating voltage is one of the most efficient ways to reduce the power dissipation of deep submicron ULSIs. A new bus architecture that reduces the operating power by using a bus signal swing of less than 1 V is proposed. This enables reduction of the bus swing to 1/3 that of the conventional architecture while maintaining a high speed and a low standby current. This architecture provides an efficient way to relieve the constraint of subthreshold leakage on V/sub CC/ scaling and to reduce the operating power of deep submicron ULSIs. Circuit configuration and performance are presented, together with experimental results.<>
Keywords :
VLSI; digital integrated circuits; 1 V; bus architecture; deep submicron; deep submicron ULSI; high speed; low standby current; low-power ULSIs; operating voltage; power dissipation; CMOS logic circuits; Circuit simulation; Delay effects; Delay estimation; Driver circuits; MOSFETs; Power dissipation; Threshold voltage; Ultra large scale integration; Variable structure systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
Type :
conf
DOI :
10.1109/VLSIC.1992.229287
Filename :
229287
Link To Document :
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