A high performance fine-grained approach to SRAM based FPGAs

This paper discusses the advantages of a reprogrammable partitioned “fine-grained” core-cell approach to FPGAs coupled with timing driven automated place and route software. Singh et al. (1992) have attempted to show that a medium to coarse cell structure and a fixed look-up table structure, is optimal for performance. Their findings were based primarily on empirical data. This paper demonstrates, that a fine grained structure, with hierarchical routing resources can achieve results which are equal to or better than the established architectures