A dual PLL based multi frequency clock distribution scheme

A clock generation scheme using two loosely coupled phase locked loops is presented. Each loop produces several clocks at different frequencies based on a single input clock. To minimize clock skew, a pipelined clock distribution structure is employed where clocks are resynchronized over multiple cycles en route to their destination. For low power applications, the design allows software to initiate a cycle-down mode, which causes all clocks to simultaneously divide down to lower frequencies by a programmable amount.<>