Title :
A high speed, segmented, SRAM based FPGA architecture for the masses
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
Intel´s FLEXlogic FPGA family is a segmented architecture, SRAM-based family with on-chip non-volatile memory. The architecture is quick to learn and easy to use for designers with standard PLD experience. Devices are organized into configurable function blocks (CFBs). Each CFB can be configured as a PLD block or as a bank of SRAM. CFBs configured as PLD blocks include advanced features that provide significant design flexibility and high integration. Truly predictable timing simplifies the design and simulation process. The inherent speed of the FLEXlogic FPGA family together with its selectable 3.3 V or 5 V I/O allows it to be used in areas where existing FPGA architectures cannot operate. The iFX780, the first member of the family, illustrates the architecture
Keywords :
SRAM chips; field programmable gate arrays; 3.3 V; 5 V; Intel FLEXlogic FPGA; PLD; SRAM; configurable function blocks; design; high speed segmented architecture; iFX780; integration; nonvolatile memory; simulation; timing; Cities and towns; Field programmable gate arrays; Logic arrays; Logic design; Logic devices; Nonvolatile memory; Pins; Process design; Random access memory; Timing;
Conference_Titel :
WESCON/'93. Conference Record,
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-9970-6
DOI :
10.1109/WESCON.1993.488456
