Hardware optimization for a reconfigurable Polyphase-FFT design using common sub-expression elimination

In this paper, the implementation of a reconfigurable polyphase-FFT circuit and its building blocks designed for low hardware complexity are presented. The polyphase-FFT circuit can be configured to support 8,16 or 32 channels where each FIR filter in the polyphase filter can be configured to have up to 15 taps. The common sub-expression elimination algorithm (CSE) has been used to reduce the number of partial products for multiplication operations in FIR filter, phase shifter, and FFT circuits. Real and complex multiplications in these building blocks have been transformed into sums of two products (STP) with view to detecting and eliminating digits shared by both terms. Circuit analysis has shown that a significant reduction in logic resources is achieved using this technique. Simulation results for the CSE-based reconfigurable polyphase-FFT circuit and its building blocks are presented and compared with conventional realizations.