DocumentCode
3268000
Title
Research on the routing algorithm of SRAM-based FPGA
Author
Haiyun, Gu ; Juyan, Xu
Author_Institution
Dept. of Electron., Southeast Univ., Nanjing, China
Volume
3
fYear
2004
fDate
18-21 Oct. 2004
Firstpage
1964
Abstract
SRAM-based FPGA, as the hardware basis of reconfigurable computing will be a significant part of reconfigurable SoC, the next generation IC product. An effective routing algorithm for FPGA is necessary for developing a design tool for R-SoC. This paper suggests a taxonomy for presenting FPGA routing algorithms, introduces and analyzes the typical algorithms of each kind, and for the most importance, concludes a generalized model for FPGA routing, including a generalized routing flow, parameters, and cost function. Particular routing algorithms can be derived from this model.
Keywords
SRAM chips; field programmable gate arrays; logic design; network routing; reconfigurable architectures; system-on-chip; SRAM-based FPGA; cost function; generalized routing flow; reconfigurable SoC; routing algorithm; Algorithm design and analysis; Cost function; Delay; Field programmable gate arrays; Hardware; Logic; Routing; Switches; Wire; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN
0-7803-8511-X
Type
conf
DOI
10.1109/ICSICT.2004.1435224
Filename
1435224
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