Title :
Xilinx EPLDs: the Dual Block Architecture
Author :
Goldberg, Jeffrey ; Ridgeway, David
Author_Institution :
Xilinx Inc., San Jose, CA, USA
Abstract :
The Xilinx 7300 family of EPLDs feature a unique solution to the dilemma of combining speed, flexibility and density-the Dual Block Architecture. The features of this architecture let designers take advantage of high speed paths when required, without sacrificing the ability to do complex functions or give up timing predictability. This capability is achieved by combining two different types of logic blocks on the same device
Keywords :
programmable logic devices; Dual Block Architecture; EPLDs; Xilinx 7300; Clocks; Decoding; Feedback; Logic design; Logic devices; Macrocell networks; Programmable logic arrays; Programmable logic devices; Registers; Timing;
Conference_Titel :
WESCON/'93. Conference Record,
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-9970-6
DOI :
10.1109/WESCON.1993.488470
