Title :
AMD´s next generation MACH 3 and 4 family optimized for flexibility, fast speed and predictable routing delay
Author_Institution :
Product Planning & Software Dev., Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
This paper describes the silicon architecture of AMD´s next generation Macro Array CMOS High Speed/High Density (MACH family of PLDs). With an advanced 0.65 μm technology and an innovative architecture, the next generation MACH family offers gate density up to 10000+ PLD gates with fixed, predictable worst-case pin-to-pin delays of 15 ns and External systems clock frequency up to 50+ MHz
Keywords :
CMOS logic circuits; programmable logic arrays; 0.65 micron; 15 ns; 50 MHz; AMD; MACH 3; MACH 4; Macro Array CMOS High Speed/High Density PLDs; clock frequency; routing delay; silicon architecture; CMOS technology; Computer architecture; Costs; Delay; Field programmable gate arrays; Logic devices; Packaging; Pins; Routing; Silicon;
Conference_Titel :
WESCON/'93. Conference Record,
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-9970-6
DOI :
10.1109/WESCON.1993.488472
