A hardware design approach of sorting for FlexRay-based clock synchronization

In automotive vehicles, the amount of electronic control units (ECUs) has been introduced on the safety-critical, powertrain, and suspension of chassis. ECUs need a safer and higher data-rate transmission protocol to deliver commands, statuses, and information. FlexRay is the one of alterative and provides a very high speed communication and fault-tolerant communication. The communication controller of FlexRay protocol is the core mechanism. We implement this design with Verilog HDL code. One of the most complicated parts of CC is the clock synchronization process (CSP) module. It synchronizes with other ECUs in the global time of the in-vehicle cluster by the time correction terms. The fault-tolerant midpoint algorithm is used to calculate the time correction terms from the list of the measured time values. Since the algorithm calculates the correction terms with the midpoint of the sorted list, we propose an improved systematic architecture of the sorting. We can increase the amount of sorting item very easy without redesign a full new sorting network. And it works perfectly with FlexRay.