DocumentCode :
3268467
Title :
Determining the optimum configuration for monolithic wafer scale integration
Author :
Panzer, Gary W.
Author_Institution :
Hughes Missile Syst. Co., Pomona, CA, USA
fYear :
1993
fDate :
28-30 Sep 1993
Firstpage :
500
Lastpage :
504
Abstract :
An analysis of the best technology implementation using 100,000 system gates was performed. Four selection criteria for each of the six technologies were chosen as; minimum circuit board area, minimum power dissipation, maximum MTBF, and the combination of these three. Categories evaluated were; 1) if cost was not a factor; 2) if minimal development cost was a factor; 3) if production cost was a factor; and 4) if the development cost amortized over the production quantity added with the production unit cost (total life cycle cost) was a factor. WSI shows up as the overall best technology implementation
Keywords :
circuit optimisation; economics; integrated circuit design; integrated circuit manufacture; integrated circuit reliability; wafer-scale integration; MTBF; development cost; minimum circuit board area; minimum power dissipation; monolithic wafer scale integration; optimum configuration; production quantity; production unit cost; selection criteria; system gates; Costs; Electronics packaging; Geometry; Integrated circuit packaging; Integrated circuit technology; Microelectronics; Power engineering and energy; Redundancy; Reliability engineering; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
WESCON/'93. Conference Record,
Conference_Location :
San Francisco, CA
ISSN :
1095-791X
Print_ISBN :
0-7803-9970-6
Type :
conf
DOI :
10.1109/WESCON.1993.488485
Filename :
488485
Link To Document :
بازگشت