PCI Express multi-lane de-skew logic design using embedded SERDES FPGA

Removing lane-to-lane skew is a very important function in a multi-channel receiver using high-speed serial protocols. This paper deals with implementation of data skew removing logic for the PCI Express protocol. We proposes 16 bit multi-lane de-skew logic to satisfy the PCI Express protocol specifications. This logic is optimized for general-purpose FPGA design. The proposed logic is verified by RTL simulation and implemented in an FPGA embedded programmable SERDES. The measured results agree well with the simulation results.