Boost converter control with ZAD for power factor correction based on FPGA

This paper shows experimental results of a boost converter for power factor correction using a quasi sliding control strategy named Zero Average Dynamic (ZAD). After defining the sliding surface, the purpose is obtain a zero average error each period of a PWM control signal, through the computation of a proper duty cycle. The controller was implemented in a FPGA using a DE2-70 board from TERASIC and Quartus II for the design. The experimental setup allows the study of the dynamic behavior. A comparison between simulations and experimental results is presented.