A new precomputation architecture of sequential logic circuits for low power

Precomputation is an optimization technique for low power. There are mainly two kinds of classical precomputation architectures, complete input disabling (CID) architecture and subset input disabling (SID) architecture. A new precomputation architecture is proposed, subset input alternately disabling (SIAD) architecture. SIAD has its precomputation logic produce both an enable signal and its inverted signal which control the two different input registers separately. Therefore, it assures that only some of the input variables change whether the precomputation logic functions or not. Compared with the traditional precomputation architecture, SID, SIAD can reduce the power dissipation further, especially in the case that the precomputation logic does not function. By using SIAD, a 16-bit comparator can reduce its power dissipation by 21% compared to that using SID in the condition that the precomputation logic does not work.