Title :
Design of a QPSK demodulator for DVB-S receiver ASIC chip
Author :
Yang, Hao ; Lin, Zhenhui ; Cai, Xiongfei
Author_Institution :
Dept. of Electron. Eng., Shanghai Jiao Tong Univ., China
Abstract :
The paper presents the design of an all-digital QPSK demodulator, a key component of a satellite digital video broadcast receiver system and chip. The demodulator includes 3 sub-components: symbol synchronization loop; carrier frequency recovery loop; carrier phase recovery loop. The demodulator has a good performance at low SNR, a low system loss and reasonable complexity. The paper presents the design of the loops in detail, and gives the simulation results at optimum coefficients. The paper also shows the results of implementation in FPGA.
Keywords :
application specific integrated circuits; circuit complexity; demodulators; digital video broadcasting; field programmable gate arrays; integrated circuit design; logic design; quadrature phase shift keying; synchronisation; television receivers; DVB-S receiver ASIC chip; FPGA; SNR; all-digital QPSK demodulator; carrier frequency recovery loop; carrier phase recovery loop; complexity; low system loss; satellite digital video broadcast receiver system; symbol synchronization loop; Application specific integrated circuits; Bit error rate; Decoding; Demodulation; Digital video broadcasting; Frequency locked loops; Frequency synchronization; Quadrature phase shift keying; Timing; Viterbi algorithm;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435252
