A 16×16+32 bit multiplication accumulator design adaptable to technology portability

Author

Lan, Jinghong ; Jia, Song ; Chen, Zhongjian ; Ji, Lijiu

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

Volume

3

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

2094

Abstract

We describe a 16×16+32 bit Multiplication ACcumulator (MAC) design, PKU_MAC16_001, which has a design flow adaptable to technology portability. A router, R-RS001, is also developed to finish the layout routing. The booth2 algorithm in decoding and the 4-2-compressor as the compress tree structure are used in the MAC design. A top down custom digital design flow is adopted to realize the MAC. Finally, the layout is routed through R-RS001, which can do the most time consuming and tedious layout works in MAC design, making it much easier to move a design to new technology.

Keywords

circuit layout CAD; integrated circuit layout; multiplying circuits; network routing; trees (mathematics); compress tree structure; layout routing; multiplication accumulator design; technology portability; top down custom digital design flow; Algorithm design and analysis; Application specific integrated circuits; Decoding; Design methodology; Digital signal processing; Graphics; Microelectronics; Microprocessors; Routing; Tree data structures;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1435257

Filename

1435257