An algorithm and design to test random access memories

A fast test generation algorithm of 7n complexity for testing RAMs, where n is the number of words, is presented. This algorithm covers 100% single cell stuck-at-1/0 faults, transition 1-to-0 and 0-to-1 faults, bridging faults between two cells (state coupling), and data retention faults. A design methodology (STD architecture) for designing large memories so that a very small test time can be achieved is also presented. The memory is partitioned into several small blocks. The memory address decoder is divided into two or more levels and designed so that in the test mode all small memory blocks can be accessed together. The hardware overhead in this approach is negligible, and a constant test time can be achieved irrespective of the memory size. The STD architecture is applicable to memory chips as well as memory boards