An insertion loss balance aware routing scheme in photonic network on chip

The paper presents a novel energy efficient routing scheme for photonic network on chip (PNoC) based on the microresonator which takes the insertion loss and the path-setup latency into consideration in order to design a high performance per watt multi-processors. The path-setup latency is a major contributor to the whole system´s latency that has something to do with queuing. And insertion loss which has impact on power consumption is closely related to the number of micro-resonators in on state. To solve the multi-objective optimization problem, we design a straight line first heuristic routing scheme. The goal of this routing scheme is to reduce the path-setup latency and insertion loss. Simulation results show that this scheme can low the latency with lower the insertion loss as little as possible.