Transistor stuck-at and delay faults detection in static and dynamic CMOS combinational gates

Author

Bruni, Luca ; Buonanno, Giacomo ; Sciuto, Donatella

Author_Institution

Dipartimento di Elettronica, Politecnico di Milano, Italy

Volume

1

fYear

1992

fDate

10-13 May 1992

Firstpage

431

Abstract

A technique for detection of delay faults in CMOS gates is presented. It is based on a testable design of CMOS gates and on an algorithm developed for detection of transistor stuck-at faults (stuck-open and stuck-on). This methodology can be applied to both static and dynamic CMOS gates, as shown by two examples. It is also shown that the test algorithm developed for fully CMOS logic can be easily applied to DOMINO CMOS circuits. However, in order to detect a very small set of stuck-on faults, it is necessary to monitor current drawn by the circuit

Keywords

CMOS integrated circuits; combinatorial circuits; fault location; integrated logic circuits; logic gates; logic testing; DOMINO CMOS circuits; current monitoring; delay faults; dynamic CMOS combinational gates; static CMOS; stuck-at faults; test algorithm; testable design; CMOS logic circuits; Circuit faults; Circuit testing; Design for testability; Electrical fault detection; Fault detection; Logic design; Logic testing; Propagation delay; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.229921

Filename

229921