DocumentCode
3268996
Title
A continuous-time reduced-sample-rate ΔΣ-pipeline ADC for broadband wireless applications
Author
Ge, Fuding ; Jalali-Farahani, Bahar ; Song, Hongjiang ; Ismail, Mohammed
Author_Institution
Arizona State Univ., Tempe
fYear
2007
fDate
5-8 Aug. 2007
Firstpage
936
Lastpage
939
Abstract
This paper presents a continuous-time 2-0 cascade delta-sigma modulator. The first stage of the modulator is a second-order continuous-time modulator with low-distortion structure. The second stage is a pipeline ADC with reduced sample rate. Matlab simulation shows it can achieve maximum SQNR of 77 dB with OSR=8 for the first stage and OSR=2 for the second stage. Circuit level implementation of the modulator is given and the effects of circuit nonideal properties, such as RC time-constant variation, finite opamp gain and bandwidth, on the modulator performance are discussed.
Keywords
delta-sigma modulation; pipelines; RC time-constant variation; analogue-digital convertors; broadband wireless applications; continuous-time reduced-sample-rate DeltaSigma-pipeline ADC; delta-sigma modulator; pipeline ADC; Bandwidth; Circuit simulation; Delta modulation; Filters; Pipelines; Signal design; Signal resolution; Topology; Transfer functions; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location
Montreal, Que.
ISSN
1548-3746
Print_ISBN
978-1-4244-1175-7
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2007.4488721
Filename
4488721
Link To Document