Two-phase clocking combined with sleep transistors reduces active leakage in low-frequency portable applications

The aggressive down-scaling in semiconductor devices implies the transistor voltage threshold reduction, which is associated with an exponential increase in sub-threshold leakage currents. For this reason, static power consumption is becoming the major issue of the newer technologies. A novel low-leakage technique (2Phi+sleep), which combines level-sensitive two-phase clocking (2Phi) with sleep transistors (sleep), is proposed and compared to the state of the art. The results of transistor- level simulations indicate that the proposed technique reduces active leakage (-22% in the evaluated design in a 90 nm process), while preserving the same capabilities of counteracting stand-by leakage as conventional sleep transistors.