A 200 Mb/s PRML read/write channel IC

Author

Parsi, K. ; Rao, Neeraj ; Burns, R. ; Chaiken, A. ; Chambers, M. ; Cheung, R. ; Forni, B. ; Harnishfeger, D. ; Jam, C. ; Kaylor, S. ; Pennell, M. ; Perez, J. ; Rohrbaugh, M. ; Ross, M. ; Stuhlmiller, G. ; Weiner, N.

Author_Institution

Motorola Inc., Tempe, AZ, USA

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

66

Lastpage

67

Abstract

The hard disk drive industry is looking at synchronous design techniques (PRML) with a view to increasing storage density. Currently the high performance commercial read/write channels use (0, 4/4) codes to achieve up to 120 Mb/s data transfer rates. This paper describes a fully integrated read/write channel IC that operates at over 200 Mb/s. The single-chip solution in 0.51 /spl mu/m BiCMOS, has 20 mm/sup 2/ die and uses 0.85 W at 200 Mb/s.

Keywords

BiCMOS integrated circuits; hard discs; maximum likelihood detection; partial response channels; 0.5 micron; 0.85 W; 200 Mbit/s; BiCMOS; PRML; data transfer rates; hard disk drive; partial response maximum likelihood; read/write channel IC; storage density; synchronous design techniques; Delay; Demodulation; Detectors; Equalizers; Frequency synthesizers; Phase locked loops; Sampling methods; Servomechanisms; Transversal filters; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488516

Filename

488516