Title :
A CMOS 6 b 200 M sample/s 3 V-supply A/D converter for a PRML read channel LSI
Author :
Tsukamoto, S. ; Dedic, I. ; Endo, T. ; Kikuta, K. ; Goto, K. ; Kobayashi, O.
Author_Institution :
Fujitsu VLSI Ltd., Aichi, Japan
Abstract :
There is a strong demand for high speed ADCs for PRML read channel LSI. Most of these ADCs are fabricated with bipolar or BiCMOS, because of high-speed operation. Conventional CMOS ADCs have 100 MSample/s conversion rate and insufficient tolerance to power supply noise. These problems are overcome by interleaved auto-zeroing (IAZ) architecture and output-swing limiting comparator (OLC). The ADCs operate at 200 MSample/s in a mixed PRML read channel LSI.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); hard discs; large scale integration; maximum likelihood detection; partial response channels; 6 bit; A/D converter; CMOS; PRML; interleaved auto-zeroing architecture; output-swing limiting comparator; partial response maximum likelihood; power supply noise; read channel LSI; Capacitance; Choppers; Frequency conversion; Hysteresis; Inverters; Large scale integration; Microelectronics; Noise reduction; Power supplies; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488518
