0.25 /spl mu/m CMOS/SIMOX gate array LSI

Author

Ino, M. ; Sawada, H. ; Nishimura, K. ; Urano, M. ; Suto, H. ; Date, S. ; Ishihara, T. ; Takeda, T. ; Kado, Y. ; Inokawa, H. ; Tsuchiya, T. ; Sakakibara, Y. ; Arita, Y. ; Izumi, K. ; Takeya, K. ; Sakai, T.

Author_Institution

NTT LSI Labs., Atsugi, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

86

Lastpage

87

Abstract

Silicon-on-insulator (SOI) devices have several advantages. Small parasitic capacitances make them useful for high-speed, low-power and low-voltage LSIs. SOI devices are soft-error free, latchup free, and have a high-density layout due to complete isolation. In this paper, we report a 0.25 /spl mu/m CMOS/SIMOX 300 kG gate array LSI using fully-depleted MOSFETs fabricated on a low-dose high-quality SIMOX substrate.

Keywords

CMOS logic circuits; SIMOX; large scale integration; logic arrays; 0.25 micron; CMOS/SIMOX technology; SOI devices; Si; fully-depleted MOSFETs; gate array LSI; low-dose SIMOX substrate; CMOS technology; Circuit faults; Frequency; Large scale integration; Mobile communication; Power dissipation; Substrates; Velocity measurement; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488525

Filename

488525