Title :
A 2.5 Gb/s 32:1/1:32 SONET mux/demux chip set
Author :
Pham, P.C. ; McDonald, J. ; McDevitt, P.
Author_Institution :
Logic IC Div., Motorola Inc., Chandler, AZ, USA
Abstract :
A synchronous optical network (SONET) OC-48 32:1 and 1:32b multiplexer (mux) and demultiplexer (demux) chip set includes a four-phase clocking architecture, a programmable read/write, a datahold signal, a current buildup output buffer, and matched output data and clock paths.
Keywords :
SONET; demultiplexing equipment; multiplexing; multiplexing equipment; optical communication equipment; 2.5 Gbit/s; SONET mux/demux chip set; current buildup output buffer; datahold signal; demultiplexer; four-phase clocking architecture; multiplexer; programmable read/write; synchronous optical network; Clocks; Impedance matching; Isolation technology; Logic; Multiplexing; Optical buffering; Photonic integrated circuits; SONET; Space technology; Timing;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488535
