2.8 Gb/s 176 mW byte-interleaved and 3.0 Gb/s 118 mW bit-interleaved 8:1 multiplexers

Author

Kurisu, M. ; Kaneko, M. ; Suzaki, T. ; Tanabe, A. ; Togo, M. ; Furukawa, A. ; Tamura, T. ; Nakajima, K. ; Yoshida, K.

Author_Institution

Syst. LSI Dev. Div., NEC Corp., Kawasaki, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

122

Lastpage

123

Abstract

2.8 Gbps/176 mW byte-interleaved and 3.0 Gbps/l18 mW bit-interleaved 8:1 multiplexers use 0.15 /spl mu/m CMOS technology. A byte-interleaving scheme divides input-registers into two symmetrical matrices to realize a high-density layout. Both chips have the same 8:1 time-division multiplexing core with a static shift-register architecture. The critical path delay is reduced by introducing dual-outputs D-FFs for the shift-registers. Bit-clock and byte-clock are precisely distributed to maximize speed. Direct interface with ECL circuits uses a negative supply of -2 V (VTT) and high-speed I/O buffers.

Keywords

CMOS digital integrated circuits; multiplexing equipment; time division multiplexing; 0.15 micron; 118 mW; 176 mW; 2.8 Gbit/s; 3.0 Gbit/s; CMOS chips; bit-interleaved multiplexer; byte-interleaved multiplexer; critical path delay; dual-outputs D-FFs; shift registers; time-division multiplexing; CMOS technology; Circuits; Delay; Frequency; Inverters; Laboratories; MOS devices; Multiplexing; National electric code; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488536

Filename

488536