2.8 Gb/s 176 mW byte-interleaved and 3.0 Gb/s 118 mW bit-interleaved 8:1 multiplexers

2.8 Gbps/176 mW byte-interleaved and 3.0 Gbps/l18 mW bit-interleaved 8:1 multiplexers use 0.15 /spl mu/m CMOS technology. A byte-interleaving scheme divides input-registers into two symmetrical matrices to realize a high-density layout. Both chips have the same 8:1 time-division multiplexing core with a static shift-register architecture. The critical path delay is reduced by introducing dual-outputs D-FFs for the shift-registers. Bit-clock and byte-clock are precisely distributed to maximize speed. Direct interface with ECL circuits uses a negative supply of -2 V (VTT) and high-speed I/O buffers.