Hole mobilities in the Si/SiGe grown on nanometer SOI of SIMOX [MOSFET example]

A SIMOX wafer has defects generated at the interface between the SOI and buried oxide. The nanometer-SOI device performance is supposed to be influenced by the crystalline quality of the SOI surface layer. In this report, Si/SiGe/Si layers on the SOI with a thickness of 7-283 nm were grown and P-type MOSFETs were fabricated on the layers. A crystalline quality evaluation was carried out for the surface layers through the I-V characteristics. The drain current decreased as the SOI thickness decreased. The effective hole mobility for the device with the thinnest 7-nm SOI was nearly 15% lower than that for the other devices. It was concluded that the 7-nm-thick SOI case could not sufficiently reduce the defect density in the SOI surface region and the 21-nm and 283-nm-thick SOI cases could promote the crystalline quality of the surface layers grown on the SOI.