A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators

Author

Mizuno, H. ; Matsuzaki, N. ; Osada, K. ; Shinbo, T. ; Ooki, N. ; Ishida, H. ; Ishibashi, K. ; Kure, T.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

152

Lastpage

153

Abstract

This cache operates at 10 mW, and 100 MHz at 1 V supply using separated bit-line memory hierarchy architecture (SBMHA) that reduces latency and power, and domino tag comparators (DTCs) that reduce dissipation of tag comparisons. On-chip caches in low-power microprocessors need high bit-ratio to reduce power. Higher bit-ratio is achieved using a larger cache. But this has the drawback of longer latency. The SBMHA hides the long latency.

Keywords

CMOS memory circuits; cache storage; memory architecture; 0.25 micron; 1 V; 10 mW; 100 MHz; 16 kB; 2 kB; 26 kbit; cache storage; domino tag comparators; high bit-ratio; latency reduction; low-power microprocessors; onchip caches; separated bit-line memory hierarchy; Delay; Energy consumption; Laboratories; Low voltage; Memory architecture; Microprocessors; Operational amplifiers; Power engineering and energy; Switches; Technical Activities Guide -TAG;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488549

Filename

488549