A 2 ns zero wait state, 32 kB semi-associative L1 cache

Author

Covino, J. ; Conner, J. ; Evans, D. ; Roberts, A. ; Robillard, M. ; Sousa, J. ; Temullo, L.

Author_Institution

Microelectron. Div., IBM Corp., Essex Junction, VT, USA

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

154

Lastpage

155

Abstract

A 32 kB, semi-associative bit dimension, L1 cache test site uses 0.5 /spl mu/m 2.5 V CMOS. The technology features an Leff of 0.25 /spl mu/m, a 7 nm Tox, shallow trench isolation, and a tungsten local interconnect. Four of the available five levels of metal are used. The cache consists of a data-storage array (DSA) macro, a content-addressable memory (CAM) macro, directory macro, and a memory built-in self-test (MBIST) state machine. Measured clock-to-DSA data-out access is 2 ns on nominal hardware. Access includes late-select generation from the CAM. The hardware cycles at access.

Keywords

CMOS memory circuits; cache storage; content-addressable storage; 0.5 micron; 2 ns; 2.5 V; 32 kB; CMOS technology; clock-to-DSA data-out access time; content-addressable memory macro; data-storage array macro; directory macro; hardware cycling; late-select generation; memory built-in self-test state machine; semi-associative bit dimension L1 cache; shallow trench isolation; tungsten local interconnect; zero wait state; CADCAM; CMOS technology; Clocks; Computer aided manufacturing; Decoding; Hardware; Isolation technology; Microelectronics; Pipeline processing; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488550

Filename

488550