• DocumentCode
    3269751
  • Title

    A reliable static-logic-based 16:1 binary-tree multiplexer in 0.18 μm CMOS

  • Author

    Shon, Kwansu ; Trung, N.T. ; Kim, Soo-Won ; Yoo, Jae-Tack

  • Author_Institution
    Korea Univ. Seoul, Seoul
  • fYear
    2007
  • fDate
    5-8 Aug. 2007
  • Firstpage
    1193
  • Lastpage
    1196
  • Abstract
    A reliable static-logic-based 16:1 binary-tree multiplexer is presented. By using robust delay compensation techniques, the multiplexer can operate properly in wide frequency range and process-and-temperature variation. The multiplexer test chip was fabricated by using 0.18-mum CMOS process and chip performance is summarized.
  • Keywords
    CMOS logic circuits; multiplexing equipment; CMOS process; binary-tree multiplexer; reliable static-logic multiplexer; robust delay compensation techniques; wavelength 0.18 micron; Added delay; Capacitance; Clocks; Delay effects; Flip-flops; Frequency; Logic design; Multiplexing; Reliability engineering; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
  • Conference_Location
    Montreal, Que.
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4244-1175-7
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2007.4488768
  • Filename
    4488768
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3269751