A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme

Author

Kuroda, T. ; Fujita, T. ; Mita, S. ; Nagamatu, T. ; Yoshioka, S. ; Sano, F. ; Norishima, M. ; Murota, M. ; Kako, M. ; Kinugawa, M. ; Kakumu, M. ; Sakurai, T.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

166

Lastpage

167

Abstract

This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 0.9 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT. Circuit techniques for dynamically varying threshold voltage reduce active power dissipation with negligible overhead in speed, standby power and chip area.

Keywords

CMOS digital integrated circuits; digital signal processing chips; discrete cosine transforms; integrated circuit design; multimedia communication; video signal processing; 0.3 micron; 0.9 V; 10 mW; 150 MHz; 2D discrete cosine transform; CMOS triple-well double-metal technology; HDTV-resolution; active power dissipation; chip area; core processor; dynamically varying threshold voltage; portable multimedia equipment; standby power; variable-threshold-voltage scheme; Amplitude modulation; CMOS technology; Circuits; Discrete cosine transforms; Fluctuations; Leakage current; MOSFETs; Power dissipation; Power supplies; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488555

Filename

488555