Title :
A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application
Author :
Mutoh, S. ; Shigematsu, S. ; Matsuya, Y. ; Fukuda, H. ; Yamada, J.
Author_Institution :
High Speed Integrated Circuits Lab., NTT LSI Labs., Kanagawa, Japan
Abstract :
A low-power digital signal processor (DSP) is the key component for battery-driven mobile phone equipment since a vast amount of data needs to be processed for multimedia use. Reduced supply voltage is a direct approach to power reduction. This 1 V DSPLSI with 26 MOPS and 1.1 mW/MOPS performance adopts a multi-threshold-voltage CMOS (MTCMOS) technique. A small embedded power-management processor decreases power during waiting periods.
Keywords :
CMOS digital integrated circuits; digital signal processing chips; integrated circuit design; mobile communication; multimedia communication; 1 V; CMOS DSP; embedded power-management processor; mobile phone application; multi-threshold voltage; multimedia use; power management technique; power reduction; reduced supply voltage; waiting periods; Circuits; Digital signal processing; Energy management; Leakage current; MOSFETs; Mobile handsets; Portable media players; Power supplies; Sleep; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3136-2
DOI :
10.1109/ISSCC.1996.488556
