Multiple instruction streams in a highly pipelined processor

In a highly pipelined processor, instruction dependencies involving both and control information often limit its potential performance. A cyclic pipeline machine allows multiple instruction streams to share these pipeline stages in time to remove the data and control dependencies. These multiple instruction streams exploit more parallelism in parallel programs. It provides an alternative architectural solution for new technologies such as GaAs and Josephson logic device, which prefer a highly pipelined architecture. The authors define the basic model of a cyclic pipeline machine, and examine the performance improvement of various configurations of cyclic pipeline machines compared to the same degree of pipelining of a conventional pipelined processor. The simulation results indicate that pipelining in the individual instruction streams increases the performance to maximize the utilization of resources in a highly pipelined processor