Design on high performance GaAs latched comparator for data conversion applications

Author

Feng, Shen ; Seitzer, Dieter

Author_Institution

Fraunhofer-Inst. for Integrated Circuits, Erlangen, Germany

Volume

1

fYear

1992

fDate

10-13 May 1992

Firstpage

228

Abstract

Design considerations for high-speed, high-precision latched comparators in data conversion applications are presented. The comparators are built using a fully differential broadband amplifier and source-coupled FET logic (SCFL) flip-flops in cascade. The limitations due to the DC offset voltage, settling time, and voltage gain of the input differential amplifier and the regeneration and recovery times of the SCFL flip-flop are discussed for GaAs E/D FET technology. A high-performance latched comparator has been implemented in a 0.5-μm HEMT technology. Its measured input sensitivity voltage has reached 2.0 mV at 1.0 GHz and 10.0 mV at 4.0 GHz

Keywords

III-V semiconductors; MMIC; differential amplifiers; digital integrated circuits; field effect integrated circuits; flip-flops; gallium arsenide; high electron mobility transistors; microwave amplifiers; semiconductor device models; 0.5 micron; 1 to 4 GHz; 2 to 10 mV; DC offset voltage; E/D FET technology; GaAs; HEMT; SCFL; data conversion applications; differential amplifier; differential broadband amplifier; input sensitivity voltage; latched comparator; limitations; recovery times; semiconductors; settling time; source-coupled FET logic; voltage gain; Data conversion; Differential amplifiers; Equivalent circuits; FETs; Flip-flops; Gallium arsenide; HEMTs; MESFETs; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.229972

Filename

229972