Stochastic inductance model of on chip active inductor

Author

Banchuin, Rawid ; Chaisricharoen, Roungsan

Author_Institution

Dept. of Comput. Eng., Siam Univ., Bangkok, Thailand

Volume

5

fYear

2010

fDate

22-24 June 2010

Abstract

In this study, the model which describes the effect of the stochastic nature of the bias current to the inductance of the on chip active inductor has been proposed. This study has been performed based on the up to dated CMOS technology. For the model derivation and verification, the fundamental concept of stochastic process and goodness of fit test have been adopted respectively. The model can accurately capture the stochastic behavior of the resulting inductance with sufficient confidence i.e. 95% with the K-S test. The proposed model is applicable to any CMOS on chip active inductor. Hence, it has been found to be a convenience tool for the design of various active inductor based communication circuits and systems as its aim.

Keywords

CMOS integrated circuits; inductance; inductors; integrated circuit modelling; stochastic processes; CMOS technology; K-S test; bias current; chip active inductor; model derivation; model verification; stochastic inductance model; Active inductors; CMOS technology; Circuit noise; Circuits and systems; Inductance; Semiconductor device modeling; Stochastic processes; Stochastic systems; System-on-a-chip; Tuning; CMOS technology; communication; noise interference; on chip active inductor; stochastic;

fLanguage

English

Publisher

ieee

Conference_Titel

Education Technology and Computer (ICETC), 2010 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6367-1

Type

conf

DOI

10.1109/ICETC.2010.5529957

Filename

5529957