DocumentCode :
3270108
Title :
A Novel NAND Flash FTL for Mass Data Storage Devices Based on Hybrid Address Translation
Author :
Xie Qiyou ; Liu Qiang ; Nie Hongshan ; Sun Zhaolin ; Zhou Li ; Song Rui
Author_Institution :
Nat. Univ. of Defense Technol., Changsha, China
fYear :
2013
fDate :
16-18 Jan. 2013
Firstpage :
150
Lastpage :
157
Abstract :
This paper presents a new NAND Flash Translation Layer, called MH-FTL, for Mass data storage devices based on Hybrid address translation, which improved the performance of mass data storage markedly. Firstly, MH-FTL decreases memory space of the address mapping table greatly by three levels address mapping method, including block group level address translation (BGAT), block level address translation (BAT) and page level address translation (PAT). Secondly, it makes the storage devices always working at its best performance through pipeline block group address mapping technology and parallel block group address mapping technology for BGAT and pipeline block address translation for BAT, all of those methods take the integrating way of multi-Flash within mass data storage devices into account. Thirdly, it uses non-associate page address translation with double threshold values to guarantee the small data write performance. Compared with the existing PAT, BAT and HAT FTL, MH-FTL´s write amplification is almost the same as PAT and HAT, but far below to BAT, the effective write speed is the best of all. Under the performance estimate condition of this paper, MH-FTL´s write speed is more than ten times fast of PAT, BAT, and HAT at most. For large data storage, the memory space occupation of address mapping table is one-sixteenth of BAT and HAT, and the small data write performance is not decreased as well.
Keywords :
flash memories; logic gates; address mapping table; block group level address translation; block level address translation; data write performance; flash translation layer; hybrid address translation; mass data storage device; memory space occupation; non-associate page address translation; novel NAND flash FTL; page level address translation; parallel block group address mapping technology; pipeline block group address mapping technology; storage device; three level address mapping method; File systems; Flash memory; Organizations; Performance evaluation; Pipeline processing; Pipelines; FTL; Hybrid Address Translation; Mass data storage; NAND Flash;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent System Design and Engineering Applications (ISDEA), 2013 Third International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4673-4893-5
Type :
conf
DOI :
10.1109/ISDEA.2012.42
Filename :
6454675
Link To Document :
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