Artificial dislocation network for Si nanodevices

With the use of SOI structure, formation of a nanometer-scale potential array is the key issue for the multi-junction SET/SHT devices. In this talk, a 2D dislocation network artificially embedded in an ultrathin SOI layer is presented. As schematically shown, the concept to use the dislocation network is to introduce a periodic stress filed in the SOI layer. As widely used in the III-V and Si/SiGe heteroepitaxial systems, the band structure can be engineered by the lattice strain (Van De Walle, 1989).