Artificial dislocation network for Si nanodevices

Author

Ishikawa, Yasuhiko ; Tabe, Michiharu

Author_Institution

Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan

fYear

2005

fDate

25-28 Oct. 2005

Firstpage

60

Lastpage

61

Abstract

With the use of SOI structure, formation of a nanometer-scale potential array is the key issue for the multi-junction SET/SHT devices. In this talk, a 2D dislocation network artificially embedded in an ultrathin SOI layer is presented. As schematically shown, the concept to use the dislocation network is to introduce a periodic stress filed in the SOI layer. As widely used in the III-V and Si/SiGe heteroepitaxial systems, the band structure can be engineered by the lattice strain (Van De Walle, 1989).

Keywords

Ge-Si alloys; III-V semiconductors; band structure; epitaxial growth; nanotechnology; screw dislocations; semiconductor materials; silicon; silicon-on-insulator; stress effects; wafer bonding; III-V system; SOI structures; Si-SiGe; artificial dislocation network; band structure; heteroepitaxial system; lattice strain; nanometer-scale potential array; periodic stress; silicon nanodevices; single electron tunneling devices; single hole tunneling devices; ultrathin SOI layer; Capacitive sensors; Electronic mail; FETs; Fasteners; Laboratories; MOSFETs; Quantum cellular automata; Resonant tunneling devices; Silicon on insulator technology; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocesses and Nanotechnology Conference, 2005 International

Print_ISBN

4-9902472-2-1

Type

conf

DOI

10.1109/IMNC.2005.203737

Filename

1595213