Title :
A 0.5V high speed DRAM charge transfer sense amplifier
Author :
Chow, Hwang-Cherng ; Hsieh, Chaung-Lin
Author_Institution :
Chang Gung Univ., Taoyuan
Abstract :
A new charge transfer sense amplifier scheme is proposed for high speed 0.5 V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.
Keywords :
DRAM chips; amplifiers; boost capacitance; cross-coupled structure; high speed DRAM charge transfer sense amplifier; voltage 0.5 V; Art; CMOS technology; Capacitance-voltage characteristics; Charge transfer; Circuit simulation; Low voltage; Parasitic capacitance; Random access memory; Signal restoration; Voltage control;
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2007.4488787
