A 10 Gb/s silicon bipolar IC for PRBS testing

Author

Kromat, O. ; Langmann, U. ; Hanke, G. ; Hillery, W.J.

Author_Institution

Lehrstuhl fur Elektronische Bauelemente, Ruhr-Univ., Bochum, Germany

fYear

1996

fDate

10-10 Feb. 1996

Firstpage

206

Lastpage

207

Abstract

The ongoing development of telecommunication circuits for the STM hierarchy is now reaching the STM 64 level(/spl sim/10 Gb/s). This creates the need for fast test circuitry. A silicon bipolar IC integrating all functions for the pseudo random binary sequence (PRBS) test of circuits and transmission systems up to 40 Gb/s is an advanced version of a previous design with limited performance. The following features are added: (1) on-chip bit error counting and PC based bit error rate evaluation and display, (2) sequence lengths switchable between 2/sup 16/-1 and 2/sup 23/-1 b (according to CCITT recommendations), (3) automatic PRBS test word synchronization of two chips for the purpose of direct external 4:1 multiplexing up to 40 Gb/s, and (4) auto-start.

Keywords

binary sequences; bipolar digital integrated circuits; circuit testing; silicon; telecommunication equipment testing; 10 Gbit/s; PRBS testing; STM hierarchy; Si; pseudo random binary sequence testing; silicon bipolar IC; telecommunication circuits; Bipolar integrated circuits; Circuit testing; Clocks; Counting circuits; Displays; Integrated circuit testing; Logic; Silicon; Synchronization; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3136-2

Type

conf

DOI

10.1109/ISSCC.1996.488573

Filename

488573