DocumentCode
3270214
Title
A quad-issue out-of-order RISC CPU
Author
Lotz, J. ; Lesartre, G. ; Naffziger, S. ; Kipp, D.
Author_Institution
Hewlett-Packard Co., Fort Collins, CO, USA
fYear
1996
fDate
10-10 Feb. 1996
Firstpage
210
Lastpage
211
Abstract
A 64 b 4-way superscalar PA-RISC microprocessor system operating from 150-250 MHz combines full out-of-order execution with low-cycle time, to produce >360 specint and >550 specfp. Specialized latching and clock circuits and extensive use of dynamic logic enable high frequency operation. 3.8 M logic transistors are integrated on a 17.68/spl times/19.1 mm/sup 2/ die in 3.3 V 0.5 /spl mu/m CMOS.
Keywords
CMOS digital integrated circuits; microprocessor chips; parallel architectures; reduced instruction set computing; 0.5 micron; 150 to 250 MHz; 3.3 V; 64 bit; CMOS chip; clock circuits; cycle time; dynamic logic; four-way superscalar PA-RISC microprocessor; high frequency operation; latching circuits; out-of-order execution; quad-issue RISC CPU; CMOS logic circuits; CMOS memory circuits; Central Processing Unit; Clocks; Delay; Frequency; Microprocessors; Out of order; Reduced instruction set computing; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-3136-2
Type
conf
DOI
10.1109/ISSCC.1996.488574
Filename
488574
Link To Document