A stereo multi-bit /spl Sigma//spl Delta/ D/A with asynchronous master-clock interface

An oversampling DAC that generates low-jitter, synchronous and oversampled clock internally uses an on-chip digital phase-locked loop (DPLL) and a digital sample-rate converter to decouple the DAC conversion rate from the audio sample rate. This allows the DAC to be driven by an independent low-jitter clock source that minimizes jitter-induced amplitude errors. The DAC uses a second-order /spl Sigma//spl Delta/ modulator in combination with a 17-level quantizer to achieve greater than 110 dB theoretical SNR and reduced out-of-band noise relative to higher-order 1b modulators. The problem of severe element matching in multi-bit DACs is addressed by applying a data-directed scrambling technique on the thermometer-decoded modulator output that modulates DAC element mismatch errors out of band.