A 1.8 V 64 MHz delta-sigma modulator for wideband and multi-standard applications

This paper presents the design and implementation of a multi-standard wideband 6^th-order delta-sigma modulator (DSM) operating at 1.8 V supply. The three-stage 6^th-order MASH (multi-stage noise shaping) DSM is proposed for operating at five different low oversampling ratios of 4, 6, 8, 12 and 16. The DSM is implemented using switched- capacitor circuits with a sampling frequency of 64 MHz. The modulator uses 3-level quantizers in each stage and features optimized noise transfer function. The signal bandwidth achieved ranges from 2 MHz to 8 MHz with resolution of 13 bits to 8 bits respectively. The power consumption of the modulator is 27.5 mW when operating at 64 MHz. The size of the core IC is around 1 mm² in a 0.18 mum single-poly, six-metal CMOS process.