A finite element-domain decomposition coupled resistance extraction method with virtual terminal insertion

In this paper, we present a finite element-domain decomposition coupled resistance extraction method to extract the on-resistance of a DMOS circuit from the layout data for the arbitrarily shaped metallization patterns. Our method aims at extracting the parasitic resistance of the source/drain metals of the DMOS circuit since its strong contribution to the total on-resistance. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. Our method also shows advantage in runtime and memory usage according to the simulation results.